Sistema Embarcado para um Monitor Holter que Utiliza o Modelo PPM na Compressão de Sinais ECG

Abstract

In this work, we present the development of an embedded system prototyping with soft-core Nios II and FPGA for a holter monitor that implements data compression, using the PPM Algorithm, and simulate ECG signals through the implementation of the Fourier series. Through a holter monitor, cardiologists can obtain ECG signals, serving as the basis for the perception of symptoms and activities of patients. These signals are captured and recorded by monitors in periods greater than or equal to 24 hours, requiring large storage size to store them, therefore increasing cost of the monitor. Using the PPM algorithm, a monitor holter can considerably reduce the size of the signals stored, thus reducing storage space and cost of device, addition to allow rapid transmission of the data. Integrating the ECG signal simulator to the device, is possible to generate samples of ECG via the embedded system, saving time and eliminating difficulties in obtaining signals, compared with the capture of real ECG signals by invasive and noninvasive methods. It enables the analysis and study of normal and abnormal ECGs. An embedded system on programmable chip (SOPC) was prototyped with a development kit containing peripherals and FPGA chip compatible with the Nios II. Architecture soft-core was set to compact operating system and software modules have been successfully developed, ported and validated on this platform.