Análise de defeitos na perspectiva do leiaute por meio de extração de elementos parasitas

Abstract

Classic fault models which represent physical faults on Integrated Circuits (IC) do not ful?ll completely current requirements for tests. Therefore, studies are being made about fault models that are based on the IC’s layout under test, instead of basing on the IC’s logical diagram, which is the technique used on classic models. Models based on layouts make possible to verify the most probable areas to happen faults in consequence of a physical defect. In this dissertation, a study is made about the main classic fault models andthemodelsbasedontheperspectiveofthelayoutwheresomeconceptsarede?ned,like: physical faults, faults, parasite elements, critical area, fault level and its correlations. After that, a fault modeling is proposed in the layout perspective and a method of extracting parasite elements of the layout is presented using CADENCE along simulational analysis and obtained results. By the end, it will be showed how parasite elements of the layout are related to the probability of fault occurrences due to the layout’s project. Satisfactory results were also obtained with respect to the layout changes to minimize the e?ects of the parasitic elements in the layout. These results show through a heat map that will demonstrate how the di?erences between the modi?ed and original layout.