Conversor A/D com amostragem não-uniforme e passo de quantização adaptativo

Abstract

In this work, we analyse different architectures of analog-to-digital converters (ADC) and propose an architecture based on sampling by crossing levels and adaptive quantization step, aiming at reducing the energy required to convert and process specific signals. The proposed architecture has parameters which can be dynamically configured by the user, as to adapt the conversion process to the signal being sampled and to the requirements of power consumption of the target application. The architecture was modeled and simulated using Matlab, and used to convert several test signals, of which an ECG signal. The use of the proposed architecture resulted in SNR improvements of up to 10dB if compared against uniform (periodic) sampling. The digital logic was implemented in FPGA from a SystemVerilog description functionally compatible with the Matlab model, and the analog part was implemented with discrete components.